1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to an analog and/or a digital circuit and a method for fabricating the same.
2. Background of the Related Art
Related art semiconductor devices will be explained with reference to the attached drawings. Recent developments in silicon processing and integrated circuit technologies require circuits which operate on lower power and voltage at a fast speed. However, when bulk silicon is used to fabricate such circuits, the benefits are limited due to short channel effects and large junction capacitance.
Such problems can be solved by using a SOI substrate. A device fabricated using the SOI, however, has problems, including a Kirk effect from floating body effect, and a low breakdown voltage due to a parasitic bipolar transistor. The floating body effect affects analog circuits more seriously than it does digital circuits. In an effort to solve these problems, different SOI related art methods have been used where a source region structure is changed, or where a field oxide film formed on the SOI is made thinner.
Referring to FIG. 1, a semiconductor device fabricated according to the first related art method is provided with an SOI substrate having a first semiconductor layer 1, a buried oxide film 2, and a second semiconductor layer 3 formed in succession. The second semiconductor layer 3 has a thickness of approximately 1500.ANG. . A gate oxide film 4 and a gate electrode 5 are stacked on a particular region of the second semiconductor layer 3, and a source region 7a and a drain region 7b are formed in the second semiconductor layer 3 on both sides of the gate electrode 5 in contact with the buried oxide film 2.
The second semiconductor layer 3 is doped with P type ions, and the gate electrode 5 and the source region 7a and the drain region 7b are heavily doped with N type ions. A surface of the second semiconductor layer 3 under the gate electrode 5 is heavily doped to form a N type impurity region 6 in contact with the source region 7a. In order to solve the problem of the floating body effect, a heavily doped P type (p.sup.+) impurity region 8 is formed so as to contact both a bottom of the heavily doped N type impurity region 6 and the source region 7a.
In other words, by causing a tunneling between the source region 7a and the heavily doped P type (p.sup.+) impurity region 8, the channel bias is set such that the source region 7a and the heavily doped P type (p.sup.+) impurity region 8 operate like a zener diode.
Referring to FIG. 2, a semiconductor device fabricated according to the second related art method has a parasitic bipolar transistor under a source region to set a body bias. The device includes a SOI substrate having a first semiconductor layer 1, a buried oxide film 2, and a second semiconductor layer 3 formed in succession. A gate oxide film 4 and a gate electrode 5 are formed on a particular portion of the second semiconductor layer 3, and a source region 7a heavily doped with N type ions is formed in a surface of the semiconductor layer 3 on one side of the gate electrode 5. A drain region (not shown), which is also heavily doped with N type ions, is formed on the other side of the gate electrode 5 in contact with the buried oxide film 2. The second semiconductor layer 3 is lightly doped with P type ions (p.sup.-), and a portion of the second semiconductor layer 3 under a central portion of the source region 7a and in contact with the buried oxide film 2 is lightly doped with N type ions (n.sup.-). Accordingly, a pnp parasitic bipolar transistor is formed under the source region 7a. A body bias can be set using the parasitic bipolar transistor.
Referring to FIG. 3, a semiconductor device fabricated according to the third related art method, in which a body bias is set by forming metal spikings in a source region, has a SOI substrate including a first semiconductor layer 1, a buried oxide film 2, and a second semiconductor layer 3 formed in succession. A gate oxide film 4 and a gate electrode 5 are stacked on a particular region, and portions of the second semiconductor layer 3 on both sides of the gate electrode 5 are heavily doped with N type ions to form a source region 7a and a drain region 7b. The second semiconductor layer 3 is then lightly doped with P type ions (p.sup.-), and the source region 7a and the drain region 7b are heavily doped with N type ions (n.sup.+). The source region 7a and the drain region 7b are both in contact with the buried oxide film 2. A heavily doped P type impurity region 8 is formed in the second semiconductor layer under the source region 7a. A protection film 10 includes contact holes to expose particular portions of the source region 7a and the drain region 7b. The contact holes are filled with aluminum interconnection layers 11. The aluminum interconnection layers 11 have irregular aluminum spikings extending into the source region 7a and the drain region 7b.
FIG. 4 shows two perspectives of a semiconductor device fabricated according to the fourth related art method. The left portion illustrates a section of the device in a channel width direction, and the right portion illustrates the device in a channel length direction. The device includes a first semiconductor layer 1 having a buried oxide film 2 formed thereon, a lightly doped P type second semiconductor layer 3 formed on the buried oxide film 2, with an active region and a filed region defined on the second semiconductor layer 3. It further includes a field oxide film 12 formed in and on a surface of the second semiconductor layer 3 defined as the field region. There is also a thin, lightly doped P type second semiconductor layer 3 under the field oxide film 12, and a gate oxide film 4 and a gate electrode 5 formed on a particular portion of the second semiconductor layer 3. Further, there are heavily doped source and drain regions 7a and 7b in the second semiconductor layer 3 on either side of the gate electrode 5. The source region 7a and the drain region 7b are in contact with the buried oxide film 2.
The aforementioned related art semiconductor devices have various problems. For example, the possibility that a body voltage will be applied only to the source region in the first, second, and third related art methods, allowing application only to a pass transistor, provides less flexibility in construction of a circuit. The first, second, and third related art methods require a separate process to set a body voltage. Further, the high possibility that latch up will occur in the fourth related art device reduces its reliability. Moreover, a digital circuit with a semiconductor device formed according to the fourth related art method does not take full advantage of the benefits of the SOI because a partial depletion type and a full depletion type are not coexistent.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.